1. Field of the Invention
This invention relates to electronic circuitry and, more particularly, to circuitry used within a system that can essentially eliminate skew in complementary signals, such as clock signals used to synchronize double data rate data output for source synchronous systems.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Electronic subsystems typically operate as synchronous systems. A synchronous system is often thought of as a system that enters one state after departing a preceding state. The impetus for transitioning between states might be, for example, a regular and periodic signal that triggers the transition. Most such signals are referred to as clocking signals. Thus, synchronous electronic systems rely upon a reliably periodic stream of clocking cycles.
Unfortunately, not all clocking signals maintain their regular and periodic cycles due, in part, to jitter and noise placed on those signals. Not only might the transitional edges of the clock signal periodically vary due to jitter and skewing effects, but when electronic subsystems rely on complementary clock signals, then any jitter on one of the complementary pair will delay one clock relative to the other. As used herein, the term “skew” refers to essentially the time difference between signals due to jitter, noise, or timing differences for logic that produce those signals.
When applied to clock signals, any clocking signal skew will change the transition point between cycles on an irregular or inconsistent basis or, possibly, on a cumulative basis. Complementary signals or complementary clock signals utilize what is known as a true signal and an inverted signal. If there is any clock skew between the true and inverted signals, then transitions on the inverted signal will occur in advance of, or be delayed relative to, the true signal.
In electronic subsystems that rely upon complementary signals in general or complementary clock signals specifically, it is desirable for the complementary clock signals to transition at the same time. If not, then transitions in the state sequence affected by the true clock signal will be skewed from transitions in the sequence affected by the inverted clock signal. Most digital sequential systems rely upon complementary clock signals and, more specifically, complementary clock signals that do not have substantial skew or delay between transitions of the true and inverted signals. It is, therefore, desirable to reduce clock skew and jitter in complementary signals used to sequentially operate electronic subsystems.